Japanese Laid-Open Patent Applications No. 6-237151 discloses a dual memory circuit to improve the reliability of the data retained in the memory circuit. The dual memory circuit includes a first latch circuit and a second latch circuit that are connected in parallel with each other. The first circuit is provided with an input terminal to operate the first latch circuit independently of the second latch circuit. This semiconductor integrated circuit device is capable of individually testing the latch circuits of the dual configuration, to ensure the merit if the dual configuration.